Essi Programming Model; Essi Control Register A (Cra); Essi Control Register A(Cra); Essi Control Register A (Cra - Motorola DSP56303 User Manual

ESSI Programming Model

7.5 ESSI Programming Model
The ESSI is composed of the following registers:
n
Two control registers (CRA, CRB), page 7-14 and page 7-18
n
One status register (SSISR), page 7-28
n
One Receive Shift Register, page 7-29
n
One Receive Data Register (RX), page 7-30
n
Three Transmit Shift Registers, page 7-30
n
Three Transmit Data Registers (TX0, TX1, TX2), page 7-30
n
One special-purpose Time Slot Register (TSR), page 7-33
n
Two Transmit Slot Mask Registers (TSMA, TSMB), page 7-33
n
Two Receive Slot Mask Registers (RSMA, RSMB), page 7-35
This section discusses the ESSI registers and describes their bits. Section 7.6, GPIO Signals
and Registers, on page 7-36 covers ESSI GPIO.
7.5.1

ESSI Control Register A (CRA)

The ESSI Control Register A (CRA) is one of two 24-bit read/write control registers that
direct the operation of the ESSI. CRA controls the ESSI clock generator bit and frame sync
rates, word length, and number of words per frame for serial data.
23 22 21
SSC1 WL2
11 10 9
PSR
—Reserved bit; read as 0; write to 0 for future compatibility.
7-14
20 19 18
WL1 WL0 ALC
8 7 6
PM7 PM6
(ESSI0 X:$FFFFB5, ESSI1 X:$FFFFA5)
Figure 7-2. ESSI Control Register A(CRA)
DSP56303 User's Manual
17 16 15
DC4 DC3
5 4 3
PM5 PM4 PM3
14 13 12
DC2 DC1 DC0
2 1 0
PM2 PM1 PM0