Hi08 Programming Model: Host Side - Motorola DSP56303 User Manual

Programming Model Quick Reference
Reg
#
ICR 0 RREQ
1 TREQ
2 HDRQ
3 HF0
4 HF1
5 HLEND Host Little Endian
7 INIT
ISR 0 RXDF
1 TXDE
2 TRDY
3 HF2
4 HF3
7 HREQ
CVR 6–0 HV[6–0] Host Command Vector
CVR 7 HC
RXH/M/L 7–0
TXH/M/L 7–0
IVR 7–0 IV[7–0]
6-34
Table 6-20. HI08 Programming Model: Host Side
Bit
Name
Receive Request Enable
Transmit Request Enable
Double Host Request
Host Flag 0
Host Flag 1
Initialize
Receive Data Register Full
Transmit Data Register
Empty
Transmitter Ready
Host Flag 2
Host Flag 3
Host Request
Host Command
Host Receive Data Register
Host Transmit Data Register
Interrupt Register
DSP56303 User's Manual
Value Function
0 HRRQ interrupt disabled
1 HRRQ interrupt enabled
0 HTRQ interrupt disabled
1 HTRQ interrupt enabled
0 HREQ/HTRQ = HREQ,
HACK/HRRQ = HACK
1 HREQ/HTRQ = HTRQ,
HACK/HRRQ = HRRQ
0 Big Endian order
1 Little Endian order
1 Reset data paths according to
TREQ and RREQ
0 Host Receive Register is empty
1 Host Receive Register is full
1 Host Transmit Register is empty
0 Host Transmit Register is full
1 transmit FIFO (6 deep) is empty
0 transmit FIFO is not empty
0 HREQ signal is deasserted
1 HREQ signal is asserted (if
enabled)
0 no host command pending
1 host command pending
68000 family vector register
Reset Type
HW/ Indivi
STOP
SW -dual
0 — —
0 — —
0 — —
0 — —
0 — —
0 — —
0 — —
0 0 0
1 1 1
1 1 1
0 — —
0 — —
0 0 0
$32 — —
0 0 0
empty
empty
$0F — —