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Operating Modes: Normal, Network, and On-Demand
7.4.5
Frame Sync Length for Multiple Devices
The ability to mix frame sync lengths is useful to configure systems in which data is received
from one type of device (for example, codec) and transmitted to a different type of device.
CRB[FSL0] controls whether RX and TX have the same frame sync length.
n
If CRB[FSL0] is cleared, both RX and TX have the same frame sync length.
n
If CRB[FSL0] is set, RX and TX have different frame sync lengths.
CRB[FSL0] is ignored when CRB[SYN] is set.
7.4.6
Word Length Frame Sync and Data Word Timing
The CRB[FSR] bit controls the relative timing of the word length frame sync relative to the
data word timing.
n
When CRB[FSR] is cleared, the word length frame sync is generated (or expected)
with the first bit of the data word.
n
When CRB[FSR] is set, the word length frame sync is generated (or expected) with the
last bit of the previous word.
CRB[FSR] is ignored when a bit length frame sync is selected.
7.4.7
Frame Sync Polarity
The CRB[FSP] bit controls the polarity of the frame sync.
n
When CRB[FSP] is cleared, the polarity of the frame sync is positive; that is, the frame
sync signal is asserted high. The ESSI synchronizes on the leading edge of the frame
sync signal.
n
When CRB[FSP] is set, the polarity of the frame sync is negative; that is, the frame
sync is asserted low. The ESSI synchronizes on the trailing edge of the frame sync
signal.
The ESSI receiver looks for a receive frame sync edge (leading edge if CRB[FSP] is cleared,
trailing edge if FSP is set) only when the previous frame is completed. If the frame sync is
asserted before the frame is completed (or before the last bit of the frame is received in the
case of a bit frame sync or a word-length frame sync with CRB[FSR] set), the current frame
sync is not recognized, and the receiver is internally disabled until the next frame sync.
Frames do not have to be adjacent; that is, a new frame sync does not have to follow the
previous frame immediately. Gaps of arbitrary periods can occur between frames. All the
enabled transmitters are tri-stated during these gaps.
7-12
DSP56303 User's Manual
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