Operation; Timer After Reset; Timer Module Block Diagram - Motorola DSP56303 User Manual

The timer mode is controlled by the TC[3–0] bits which are TCSR[7–4]. For a listing of the
timer modes and descriptions of their operations, see Section 9.3, Operating Modes, on page
9-5.
.
GDB
Control/Status
Register
Timer Control
Logic
TIO CLK/2
9.2

Operation

This section discusses the following timer basics:
n
Reset
n
Initialization
n
Exceptions
9.2.1

Timer After Reset

A hardware signal or software RESET instruction clears the Timer Control and Status
RESET
Register for each timer, thus configuring each timer as a GPIO. A timer is active only if the
timer enable bit 0 (TCSR[TE]) in the specific timer TCSR is set.
24
24 24
TCSR
TLR
Load
Register
9
2
Prescaler CLK
Figure 9-2. Timer Module Block Diagram
Triple Timer Module
24
TCR
Count
Register
24 24
24
Counter
Timer interrupt/DMA request
Operation
24
TCPR
Compare
Register
24
=
9-3