Dma Control Registers 5-0 (Dcr[5-0; B-9 Dma Control Registers 5–0 (Dcr[5–0]) - Motorola DSP56303 User Manual

Programming Sheets
Application:
DMA Channel Enable, Bit 23
0 = Disables channel operation
1 = Enables channel operation
DMA Interrupt Enable, Bit 22
0 = Disables DMA Interrupt
1 = Enables DMA interrupt
DMA Transfer Mode, Bits 21–19
DTM[2:0] Triggered By
000 request
001 request
010 request
011 DE
100 request
101 request
110 reserved
111 reserved
DMA Channel Priority, Bits 18–17
DPR[1:0]
00
01
10
11
DMA Continuous Mode Enable, Bit 16
0 = Disables continuous mode
1 = Enables continuous mode
DMA Request Source, Bits 15–11
DRS[4:0]
00000–00011
00100–01001
01010–01011
01100–01101
01110–01111
10000–10010
10011
10100
10101 - 11111
23 22 21 20
DE DIE DTM[2–0]
DMA Control Registers (DCR5–DCR0)
Reset = $000000
B-20
DE Cleared Transfer Mode
yes block transfer
yes word transfer
yes line transfer
yes block transfer
no block transfer
no word transfer
Channel Priority
Priority level 0 (lowest)
Priority level 1
Priority level 2
Priority level 3 (highest)
Requesting Device
External (IRQA, IRQB, IRQC, IRQD)
Transfer done from channel 0,1,2,3,4,5
ESSI0 Receive, Transmit Data
ESSI1 Receive, Transmit Data
SCI Receive, Transmit Data
Timer0, Timer1, Timer2
Host Receive Data Full
Host Transmit Data Empty
Reserved
19 18 17 16 15 14 13 12 11 10 9
DPR[1–0] DCON DRS[4–0]
Figure B-9. DMA Control Registers 5–0 (DCR[5–0])
DSP56303 User's Manual
Three-Dimensional Mode, Bit 10
0 = Three-Dimensional mode disabled
1 = Three-Dimensional mode enabled
DMA Address Mode, Bits 9–4
Non-Three-Dimensional Addressing Modes (D3D=0)
DAM[2–0] = source
DAM[5:3] Addressing Mode
DAM[2:0]
000 2D
001 2D
010 2D
011 2D
100 No update
101 Postincrement-by-1
110 reserved
111 reserved
Three-Dimensional Addressing Modes (D3D=1)
DAM[5:3]
000 2D
001 2D
010 2D
011 2D
100 No update
101 Postincrement-by-1
110 3D
111 3D
DMA Destination Space, Bits 3–2
DSS[1:0]
DMA Source Space, Bits 1–0
DSS[1:0]
8 7
D3D DAM[5–0]
X:$FFFFD8, X:$FFFFDC, X:$FFFFE0,
X:$FFFFE4, X:$FFFFE8, X:$FFFFEC
Date:
Programmer:
Sheet 1 of 1
DMA
DAM[5–3] = Destination
Counter Offset Register
Mode Selection
B DOR0
B DOR1
B DOR2
B DOR3
A None
A None
Addressing Mode Offset Selection
DOR0
DOR1
DOR2
DOR3
None
None
DOR0: DOR1
DOR2: DOR3
DMA Destination Memory
00 X Memory Space
01 Y Memory Space
10 P Memory Space
11 Reserved
DMA Source Memory
00 X Memory Space
01 Y Memory Space
10 P Memory Space
11 Reserved
6 5 4 3 2 1
DDS[1–0] DSS[1–0]
Read/Write
0