Core Configuration - Motorola DSP56303 User Manual

Chapter 4

Core Configuration

This chapter presents DSP56300 core configuration details specific to the DSP56303,
including:
n
Operating modes
n
Bootstrap program
n
Central Processor registers
— Status register (SR)
— Operating mode register (OMR)
n
Interrupt Priority Registers (IPRC and IPRP)
n
PLL control (PCTL) register
n
Bus Interface Unit registers
— Bus Control Register (BCR)
— DRAM Control Register (DCR)
— Address Attribute Registers (AAR[3–0])
n
DMA Control Registers 5–0 (DCR[5–0])
n
Device identification register (IDR)
n
JTAG identification register
n
JTAG boundary scan register (BSR)
For information on specific registers or modules in the DSP56300 core, refer to the
DSP56300 Family Manual.
Core Configuration
4-1