Software Polling; Core Interrupts And Host Commands - Motorola DSP56303 User Manual

in the following sections. The transfers described here occur asynchronously between the host
and the DSP; each transferring data at its own pace. However, use of the appropriate
handshaking protocol allows data transfers to occur at optimum rates.
6.4.1

Software Polling

Software polling is the simplest data transfer method to use, but it demands the greatest
amount of the core's processing power. Status bits are provided for the host or the DSP core
to test and determine if the data registers are empty or full. However, the DSP core cannot be
involved in other processing activities while it is polling these status bits.
On the DSP side, for transfers from the DSP to the host (host reads), the DSP core must
determine the state of Host Transmit Data register (HTX). In transfers from the host to the
DSP (host writes), the DSP side should determine the state of the Host Receive Data Register
(HRX). Thus, two bits are provided to the core for polling:
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the Host Transmit Data Empty (HTDE) bit in the Host Status register (HSR[1]:HTDE)
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the Host Receive Data Full (HRDF) bit in the Host Status register (HSR[0]:HRDF)
A similar mechanism is available on the host-side to determine the state of the Transmit
Registers (TXH:TXM:TXL) and Receive Registers (RXH:RHM:RHL). Two bits are
provided to the host for polling:
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the Transmit Data Empty (TXDE) bit in the Interface Status Register (ISR[1]:TXDE)
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the Receive Data Full (RXDF) bit in the Interface Status Register (ISR[0]:RXDF)
The HI08 also offers four general-purpose flags for communication between the host and the
DSP. The DSP-side uses the HSR Host Flag bits (HCR[4–3]=HF[3–2]) to pass
application-specific information to the host. The status of HF3–HF2 is reflected in the
host-side ISR Host Flag bits (ISR[4–3]=HF[3–2]). Similarly, the host side can use the ICR
Host Flag bits (ICR[4–3]=HF[1–0]) to pass application-specific information to the DSP. The
status of HF[1–0] is reflected in the DSP-side HSR Host Flag bits
(HSR[4–3]=HF[1–0]).
6.4.2

Core Interrupts and Host Commands

The HI08 can request interrupt service from the DSP56303 core. The DSP56303 core
interrupts are internal and do not require the use of an external interrupt signal. When the
appropriate interrupt enable bit in the HCR is set, an interrupt condition caused by the host
interface sets the appropriate bit in the HSR, generating an interrupt request to the DSP56303
interrupt controller (see Figure 6-2). The DSP56303 acknowledges interrupts by jumping to
the appropriate interrupt service routine. The following DSP core interrupts are possible from
the HI08 peripheral:
Host Interface (HI08)
Operation
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