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Module
Central
Figure B-1, "Status Register (SR)"
Processor
Figure B-2, "Operating Mode Register (OMR)"
IPR
Figure B-3, "Interrupt Priority Register-Core (IPRC)"
Figure B-4, "Interrupt Priority Register-Peripherals (IPRP)"
PLL
Figure B-5, "Phase-Locked Loop Control Register (PCTL)"
BIU
Figure B-6, "Bus Control Register (BCR)"
Figure B-7, "DRAM Control Register (DCR)"
Figure B-8, "Address Attribute Registers (AAR[3–0])"
DMA
Figure B-9, "DMA Control Registers 5–0 (DCR[5–0])"
HI08
Figure B-10, "Host Transmit Data Register"
Figure B-11, "Host Base Address and Host Port Control Registers"
Figure B-12, "Host Control Register"
Figure B-13, "Interrupt Control and Command Vector Registers"
Figure B-14, "Interrupt Vector and Host Transmit Data Registers"
ESSI
Figure B-15, "ESSI Control Register A (CRA)"
Figure B-16, "ESSI Control Register B (CRB)"
Figure B-17, "ESSI Transmit and Receive Slot Mask Registers (TSM, RSM)"
SCI
Figure B-18, "SCI Control Register (SCR)"
Figure B-19, "SCI Clock Control Registers (SCCR)"
Timers
Figure B-20, "Timer Prescaler Load Register (TPLR)"
Figure B-21, "Timer Control/Status Register (TCSR)"
Figure B-22, "Timer Load Registers (TLR)"
GPIO
Figure B-23, "Host Data Direction and Host Data Registers (HDDR, HDR)"
Figure B-24, "Port C Registers (PCRC, PRRC, PDRC)"
Figure B-25, "Port D Registers (PCRD, PRRD, PDRD)"
Figure B-26, "Port E Registers (PCRE, PRRE, PDRE)"
B-2
Table B-1. Guide to Programming Sheets
Programming Sheet
DSP56303 User's Manual
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