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GPIO Signals and Registers
7.6
GPIO Signals and Registers
The functionality of each ESSI port is controlled by three registers: port control register
(PCRC, PCRD), port direction register (PRRC, PRRD), and port data register (PDRC,
PDRD).
7.6.1
Port Control Registers (PCRC and PCRD)
The read/write 24-bit PCRs control the functionality of the signal lines for ESSI0 and ESSI1.
Each of the PCR bits 5–0 controls the functionality of the corresponding signal line. When a
PCR[i] bit is set, the corresponding port signal is configured as an ESSI signal. When a
PCR[i] bit is cleared, the corresponding port signal is configured as a GPIO signal. Either a
hardware
signal or a software RESET instruction clears all PCR bits.
RESET
23
22
21
11
10
9
Note:
For Px[5–0], a 0 selects Pxn as the signal and a 1 selects the specified ESSI signal. For ESSI0, the GPIO
signals are PC[5–0] and the ESSI signals are STD0, SRD0, SCK0, and SC0[2–0]. For ESSI1, the GPIO
signals are PD[5–0] and the ESSI signals are STD1, SRD1, SCK1, and SC1[2–0].
= Reserved. Read as zero. Write with zero for future compatibility.
Figure 7-18. Port Control Registers (PCRC X:$FFFFBF) (PCRD X:$FFFAF)
7-36
20
19
18
8
7
6
DSP56303 User's Manual
17
16
15
5
4
3
PCx5
PCx4
PCx3
14
13
12
2
1
0
PCx2
PCx1
PCx0
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