Motorola DSP56303 User Manual page 9

24-bit digital signal processor
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7.5.7 ESSI Transmit Data Registers (TX[2-0])............................................................................ 7-33
7.5.8 ESSI Time Slot Register (TSR) ........................................................................................... 7-33
7.5.9 Transmit Slot Mask Registers (TSMA, TSMB) .................................................................. 7-33
7.5.10 Receive Slot Mask Registers (RSMA, RSMB) ................................................................... 7-35
7.6
GPIO Signals and Registers................................................................................................. 7-36
7.6.1 Port Control Registers (PCRC and PCRD).......................................................................... 7-36
7.6.2 Port Direction Registers (PRRC and PRRD)....................................................................... 7-37
7.6.3 Port Data Registers (PDRC and PDRD).............................................................................. 7-38
8
Chapter
8.1
Operating Modes.................................................................................................................... 8-1
8.1.1 Synchronous Mode ................................................................................................................ 8-2
8.1.2 Asynchronous Mode .............................................................................................................. 8-2
8.1.3 Multidrop Mode ..................................................................................................................... 8-2
8.1.3.1
Transmitting Data and Address Characters ..................................................................... 8-3
8.1.3.2
Wired-OR Mode .............................................................................................................. 8-3
8.1.3.3
Idle Line Wakeup............................................................................................................. 8-3
8.1.3.4
Address Mode Wakeup.................................................................................................... 8-3
8.2
I/O Signals ............................................................................................................................. 8-3
8.2.1 Receive Data (RXD) .............................................................................................................. 8-4
8.2.2 Transmit Data (TXD)............................................................................................................. 8-4
8.2.3 SCI Serial Clock (SCLK) ...................................................................................................... 8-4
8.3
SCI After Reset ...................................................................................................................... 8-5
8.4
SCI Initialization.................................................................................................................... 8-6
8.4.1 Preamble, Break, and Data Transmission Priority................................................................. 8-7
8.4.2 Bootstrap Loading Through the SCI (Boot Mode 2 or A)..................................................... 8-8
8.5
Exceptions.............................................................................................................................. 8-8
8.6
SCI Programming Model....................................................................................................... 8-9
8.6.1 SCI Control Register (SCR) ................................................................................................ 8-12
8.6.2 SCI Status Register (SSR) ................................................................................................... 8-17
8.6.3 SCI Clock Control Register (SCCR) ................................................................................... 8-19
8.6.4 SCI Data Registers............................................................................................................... 8-22
8.6.4.1
SCI Receive Register (SRX).......................................................................................... 8-22
8.6.4.2
SCI Transmit Register (STX) ........................................................................................ 8-23
8.7
GPIO Signals and Registers................................................................................................. 8-24
8.7.1 Port E Control Register (PCRE) .......................................................................................... 8-24
8.7.2 Port E Direction Register (PRRE) ....................................................................................... 8-25
8.7.3 Port E Data Register (PDRE)............................................................................................... 8-25
9
Chapter
9.1
Overview................................................................................................................................ 9-1
9.1.1 Triple Timer Module Block Diagram .................................................................................... 9-2
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