Command Vector Register (Cvr) - Motorola DSP56303 User Manual

Host Programmer Model
Table 6-15. Interface Control Register (ICR) Bit Definitions (Continued)
Bit Number Bit Name
1 TREQ
0 RREQ
6.7.2

Command Vector Register (CVR)

The host processor uses the CVR, an 8-bit read/write register, to cause the DSP56303 to
execute an interrupt. The host command feature is independent of any of the data transfer
mechanisms in the HI08. It causes execution of any of the 128 possible interrupt routines in
the DSP core. Hardware, software, individual, and stop resets clear the CVR bits.
6-26
Reset Value
0 Transmit Request Enable
Enables host requests via the host request (HREQ or HTRQ) signal when
the transmit data register empty (TXDE) status bit in the ISR is set. If
TREQ is cleared, TXDE interrupts are disabled. If TREQ and TXDE are
set, the host request signal is asserted.
TREQ
0
0
1
1
TREQ
0
0
1
1
0 Receive Request Enable
Controls the HREQ signal for host receive data transfers. RREQ enables
host requests via the host request (HREQ or HRRQ) signal when the
receive data register full (RXDF) status bit in the ISR is set. If RREQ is
cleared, RXDF interrupts are disabled. If RREQ and RXDF are set, the
host request signal (HREQ or HRRQ) is asserted.
7 6 5 4
HC HV6 HV5 HV4
Figure 6-16. Command Vector Register (CVR)
DSP56303 User's Manual
Description
TREQ and RREQ modes (HDRQ = 0)
RREQ
0 No interrupts (polling)
1 RXDF request (interrupt)
0 TXDE request (interrupt)
1 RXDF and TXDE request (interrupts)
TREQ and RREQ modes (HDRQ = 1)
RREQ HTRQ Signal
0 No interrupts
(polling)
1 No interrupts
(polling)
0 TXDE request
(interrupt)
1 TXDE request
(interrupt)
3 2 1
HV3 HV2 HV1 HV0
HREQ Signal
HRRQ Signal
No interrupts
(polling)
RXDF request
(interrupt)
No interrupts
(polling)
RXDF request
(interrupt)
0