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DSP56300 Core Functional Blocks
1.5.1
Data ALU
The data ALU performs all the arithmetic and logical operations on data operands in the
DSP56300 core. These are the components of the data ALU:
Fully pipelined 24
Bit field unit, comprising a 56-bit parallel barrel shifter (fast shift and normalization;
bit stream generation and parsing)
Conditional ALU instructions
Software-controllable 24-bit, 48-bit, or 56-bit arithmetic support
Four 24-bit or 48-bit input general-purpose registers: X1, X0, Y1, and Y0
Six data ALU registers (A2, A1, A0, B2, B1, and B0) that are concatenated into two
general-purpose, 56-bit accumulators, A and B, accumulator shifters
Two data bus shifter/limiter circuits
1.5.1.1 Data ALU Registers
The data ALU registers are read or written over the X data bus and the Y data bus as 16- or
32-bit operands. The source operands for the data ALU can be 16, 32, or 40 bits and always
originate from data ALU registers. The results of all data ALU operations are stored in an
accumulator. Data ALU operations are performed in two clock cycles in a pipeline so that a
new instruction can be initiated in every clock cycle, yielding an effective execution rate of
one instruction per clock cycle. The destination of every arithmetic operation can be a source
operand for the immediately following operation without penalty.
1.5.1.2 Multiplier-Accumulator (MAC)
The MAC unit comprises the main arithmetic processing unit of the DSP56300 core and
performs all of the calculations on data operands. For arithmetic instructions, the unit accepts
as many as three input operands and outputs one 56-bit result of the following form:
extension:most significant product:least significant product (EXT:MSP:LSP).
The multiplier executes 24-bit 24-bit parallel, fractional multiplies between
twos-complement signed, unsigned, or mixed operands. The 48-bit product is right-justified
and added to the 56-bit contents of either the A or B accumulator. A 56-bit result can be
stored as a 24-bit operand. The LSP is either truncated or rounded into the MSP. Rounding is
performed if specified.
1-6
24-bit parallel multiplier-accumulator
DSP56303 User's Manual
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