Host-Side Registers After Reset - Motorola DSP56303 User Manual

Note: The external host should never write to the TXH:TXM:TXL registers if the
ISR[TXDE] bit is cleared.
Note: When data is written to a peripheral device, there is a two-cycle pipeline delay until
any status bits affected by this operation are updated. If you read any of those status
bits within the next two cycles, the bit will not reflect its current status. For details,
see Section 5.4.1, Polling, on page 5-3.
6.7.7

Host-Side Registers After Reset

Table 6-18 shows the result of the four kinds of reset on bits in each of the HI08 registers
seen by the host processor. To cause a hardware reset, assert the
software reset, execute the RESET instruction. To reset the HEN bit individually, clear the
HPCR[HEN] bit. To cause a stop reset, execute the STOP instruction.
Register Register
Name Data
ICR All bits
CVR
HV[0–6]
ISR HREQ
HF3 -HF2
TRDY
TXDE
RXDF
IVR IV[0–7]
RX RXH:RXM:RXL
TX TXH:TXM:TXL
Note: A long dash (—) denotes that the bit value is not affected by the specified reset.
Table 6-18. Host-Side Registers After Reset
HW
Reset
0
HC 0
$32
0
0
1
1
0
$0F
empty
empty
Host Interface (HI08)
RESET
Reset Type
SW
Individual Reset
Reset
0 —
0 0
$32 —
0 1 if TREQ is set;
0 otherwise
0 —
1 1
1 1
0 0
$0F —
empty empty
empty empty
Host Programmer Model
signal. To cause a
STOP
—
0
—
1 if TREQ is set;
0 otherwise
—
1
1
0
—
empty
empty
6-31