Host Receive (Hrx) Register; Dsp-Side Registers After Reset - Motorola DSP56303 User Manual

DSP Core Programming Model
6.6.8

Host Receive (HRX) Register

The HRX register is used in host-to-DSP data transfers. The DSP56303 views it as a 24-bit
read-only register. Its address is X:$FFFFC6. It is loaded with 24-bit data from the transmit
data registers (TXH:TXM:TXL on the host side) when both the transmit data register empty
(ISR[TXDE]) on the host side and host receive data full (HSR[HRDF]) on the DSP side are
cleared. The transfer operation sets both ISR[TXDE] and HSR[HRDF]. When the
HSR[HRDF] is set, the HRX register contains valid data. The DSP56303 can set the
HCR[HRIE] to cause a host receive data interrupt when HSR[HRDF] is set. When the
DSP56303 reads the HRX register, the HSR[HRDF] bit is cleared.
Note: The DSP56303 should never try to read the HRX register if the HSR[HRDF] bit is
already cleared.
6.6.9

DSP-Side Registers After Reset

Table 6-13 shows the results of the four reset types on the bits in each of the HI08 registers
accessible to the DSP56303. The hardware reset (HW) is caused by the
software reset (SW) is caused by execution of the RESET instruction. The individual reset
(IR) occurs when HPCR[HEN] is cleared. The stop reset (ST) occurs when the STOP
instruction executes.
Register Register
Name
HCR
HPCR
HSR
HBAR BA[10–3]
HDDR DR[15–0]
HDR
HRX HRX [23–0]
HTX HTX [23–0]
Note: A long dash (—) denotes that the bit value is not affected by the specified reset.
6-22
Table 6-13. DSP-Side Registers After Reset
HW
Data
Reset
All bits 0
All bits 0
HF[1–0] 0
HCP 0
HTDE 1
HRDF 0
$80
0
D[15–0] —
empty
empty
DSP56303 User's Manual
RESET
Reset Type
SW IR
Reset Reset
0 —
0 —
0 —
0 0
1 1
0 0
$80 —
0 —
— —
empty empty
empty empty
signal. The
ST
Reset
—
—
—
0
1
0
—
—
—
empty
empty