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2.1
Power
Power Name
V
PLL Power—V
CCP
well-regulated and the input should be provided with an extremely low impedance path to the V
power rail.
V
(4)
Quiet Power—An isolated power for the internal processing logic. This input must be tied externally
CCQ
to all other chip power inputs, except for V
capacitors.
V
(4)
Address Bus Power—An isolated power for sections of the address bus I/O drivers. This input
CCA
must be tied externally to all other chip power inputs, except for V
adequate external decoupling capacitors.
V
(4)
Data Bus Power—An isolated power for sections of the data bus I/O drivers. This input must be tied
CCD
externally to all other chip power inputs, except for V
decoupling capacitors.
V
(2)
Bus Control Power—An isolated power for the bus control I/O drivers. This input must be tied
CCC
externally to all other chip power inputs, except for V
decoupling capacitors.
V
Host Power—An isolated power for the HI08 I/O drivers. This input must be tied externally to all
CCH
other chip power inputs, except for V
capacitors.
V
(2)
ESSI, SCI, and Timer Power—An isolated power for the ESSI, SCI, and timer I/O drivers. This input
CCS
must be tied externally to all other chip power inputs, except for V
adequate external decoupling capacitors.
Note:
These designations are package-dependent. Some packages connect all V
other internally. On those packages, all power input except V
indicated in this table are minimum values; the total V
Table 2-2. Power Inputs
dedicated for use with Phase Lock Loop (PLL). The voltage should be
CC
CCP
. The user must provide adequate external decoupling
CCP
Signals/Connections
Description
. The user must provide adequate external decoupling
. The user must provide
CCP
. The user must provide adequate external
CCP
. The user must provide adequate external
CCP
. The user must provide
CCP
inputs except V
CC
are labeled V
CCP
CC
connections are package-dependent.
CC
Power
CC
to each
CCP
. The numbers of connections
2-3
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