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Programming Sheets
Application:
Bus Interface Unit
NOTE: All DCR bits are read/write control bits.
Refresh Prescaler, Bit 23
0 = Prescaler bypassed
1 = Divide-by-64 prescaler used
Refresh Request Rate, Bits 22–15
These read/write control bits define
the refresh request rate. The bits
specify a divide from 1–256
(BRF[7–0] = $00–$FF). A refresh
request is generated every time
the refresh counter reaches zero,
if the refresh counter is enabled
(i.e., BREN = 1).
23 22 21 20
19 18 17 16
BRP
BRF[7–0]
DRAM Control Register (DCR)
Reset = $000000
B-18
Bus Software Triggered
Refresh, Bit 14
0 = Refresh complete/reset
1 = Software triggered refresh request
Bus Refresh
Enable, Bit 13
0 = Disable
1 = Enable
Bus Mastership
Enable, Bit 12
0 = Disable
1 = Enable
15 14 13 12 11 10 9
BSTR BREN BME BPLE
X:$FFFFFA Read/Write
Figure B-7. DRAM Control Register (DCR)
DSP56303 User's Manual
Date:
Programmer:
Bus Row Out-of-Page
Wait States, Bits 3–2
00 = 4 wait states
01 = 8 wait states
10 = 11 wait states
11 = 15 wait states
Bus Page Logic
Enable, Bit 11
0 = Disable
1 = Enable
Bus DRAM Page Size, Bits 9–8
00 = 9-bit column width, 512
01 = 10-bit column width, 1 K
10 = 11-bit column width, 2 K
11 = 12-bit column width, 4 K
8
7
6
BPS[1–0]
*
*
*
0
0
0
*
= Reserved, Program as 0
Sheet 2 of 3
Bus In-Page
Wait States, Bits 1–0
00 = 1 wait state
01 = 2 wait states
10 = 3 wait states
11 = 4 wait states
5
4
3
2
1
0
BRW[1–0]
BCW[1–0]
*
*
0
0
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