Dsp56300 Core Functional Blocks - Motorola DSP56303 User Manual

— On-chip memory-expandable hardware stack
— Nested hardware DO loops
— Fast auto-return interrupts
Direct Memory Access (DMA)
— Six DMA channels supporting internal and external accesses
— One-, two-, and three- dimensional transfers (including circular buffering)
— End-of-block-transfer interrupts
— Triggering from interrupt lines and all peripherals
Phase Lock Loop (PLL)
— Allows change of low power Divide Factor (DF) without loss of lock
— Output clock with skew elimination
Hardware debugging support
— On-Chip Emulation (OnCE) module
— Joint Test Action Group (JTAG) Test Access Port (TAP)
— Address Trace mode reflects internal Program RAM accesses at the external port
Reduced power dissipation
— Very low-power CMOS design
— Wait and stop low-power standby modes
— Fully-static design specified to operate down to 0 Hz (dc)
— Optimized power-management circuitry (instruction-dependent,
peripheral-dependent, and mode-dependent)
1.5

DSP56300 Core Functional Blocks

The functional blocks of the DSP56300 core are:
Data arithmetic logic unit (ALU)
Address generation unit
Program control unit
PLL and clock oscillator
JTAG TAP and OnCE module
Memory
In addition, the DSP56303 provides a set of on-chip peripherals, discussed in Section 1.8,
Peripherals, on page 1-12.
Overview
DSP56300 Core Functional Blocks
1-5