Motorola DSP56303 User Manual page 243

Table 9-3. Timer Control/Status Register (TCSR) Bit Definitions (Continued)
Bit Number Bit Name
7–4 TC[3–0]
3
Reset Value
0 Timer Control
Control the source of the timer clock, the behavior of the TIO signal, and
the Timer mode of operation. Section 9.3,
page 9-5 describes the timer operating modes in detail.
NOTE: To ensure proper operation, the TC[3–0] bits should be changed
only when the timer is disabled (that is, when the TCSR[TE] bit is cleared)
NOTE: If the clock is external, the counter is incremented by the transitions
on the TIO signal. The external clock is internally synchronized to the
internal clock, and its frequency should be lower than the internal
operating frequency divided by 4 (that is, CLK/4).
Bit Settings
TC3 TC2
0 0
0 0
0 0
0 0
0 1
0 1
0 1
0 1
1 0
1 0
1 0
1 0
1 1
1 1
1 1
1 1
Note 1: The GPIO function is enabled only if all of the TC[3–0] bits are 0.
0 Reserved. Write to zero for future compatibility.
Triple Timer Module
Triple Timer Module Programming Model
Description
Mode Characteristics
Mode
TC1 TC0
Number
0 0 0
0 1 1
1 0 2
1 1 3 Event counter
0 0 4
measurement
0 1 5
measurement
1 0 6 Capture event
1 1 7
0 0 8
0 1 9
1 0 10
1 1 11
0 0 12
0 1 13
1 0 14
1 1 15
Operating Modes
, on
Mode
TIO Clock
Function
Timer and
1
Internal
GPIO
GPIO
Timer pulse Output Internal
Timer toggle Output Internal
Input External
Input width
Input Internal
Input period
Input Internal
Input Internal
Pulse width
Output Internal
modulation
Reserved — —
Watchdog
Output Internal
pulse
Watchdog
Output Internal
Toggle
Reserved — —
Reserved — —
Reserved — —
Reserved — —
Reserved — —
9-31