Dsp Core Programming Model; Host Control Register (Hcr) - Motorola DSP56303 User Manual

The bootstrap program then expects the following data sequence when the user program is
downloaded from the HI08:
1. Three bytes (least significant byte first) indicating the number of 24-bit program words to
be loaded.
2. Three bytes (least significant byte first) indicating the 24-bit starting address in P-memory
to load the user's program.
3. The user program (three bytes, least significant byte first, for each program word).
Once the bootstrap program finishes loading the specified number of words, it jumps to the
specified starting address and executes the loaded program.
6.6

DSP Core Programming Model

The DSP56300 core treats the HI08 as a memory-mapped peripheral occupying eight 24-bit
words in X data memory space. The DSP can use the HI08 as a normal memory-mapped
peripheral, employing either standard polled or interrupt-driven programming techniques.
Separate transmit and receive data registers are double-buffered to allow the DSP and host
processor to transfer data efficiently at high speed. Direct memory mapping allows the
DSP56303 core to communicate with the HI08 registers using standard instructions and
addressing modes. In addition, the MOVEP instruction allows direct data transfers between
DSP56303 internal memory and the HI08 registers or vice versa.
There are two types of host processor registers, data and control, with eight registers in all.
The DSP core can access all eight registers, but the external host cannot. The following data
registers are 24-bit registers used for high-speed data transfers by the DSP core.
n
Host data receive register (HRX), on page 6-22
n
Host data transmit register (HTX), on page 6-21
The DSP-side control registers are 16-bit registers that control HI08 functionality:
n
Host control register (HCR), on page 6-14
n
Host status register (HSR), on page 6-15
n
Host GPIO data direction register (HDDR), on page 6-16
n
Host GPIO data register (HDR), on page 6-16
n
Host base address register (HBAR), on page 6-17
n
Host port control register (HPCR), on page 6-18
Both hardware and software resets disable the HI08. After a reset, the HI08 signals are
configured as GPIO and disconnected from the DSP56300 core (that is, the signals are left
floating).
Host Interface (HI08)
DSP Core Programming Model
6-13