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SCI Programming Model
Table 8-2. SCI Control Register (SCR) Bit Definitions (Continued)
Bit
Reset
Bit Name
Number
Value
2–0
WDS[2–0]
8-16
0
Word Select
Select the format of transmitted and received data. Asynchronous modes are
compatible with most UART-type serial devices, and they support standard RS-232
communication links. Multidrop Asynchronous mode is compatible with the MC68681
DUART, the M68HC11 SCI interface, and the Intel 8051 serial interface. Synchronous
data mode is essentially a high-speed shift register for I/O expansion and stream-mode
channel interfaces. You can synchronize data by using a gated transmit and receive
clock compatible with the Intel 8051 serial interface mode 0. When odd parity is
selected, the transmitter counts the number of ones in the data word. If the total is not
an odd number, the parity bit is set, thus producing an odd number. If the receiver
counts an even number of ones, an error in transmission has occurred. When even
parity is selected, an even number must result from the calculation performed at both
ends of the line, or an error in transmission has occurred.
WDS2
WDS1
0
0
0
0
0
1
1
1
1
0
1
0
1
1
0
1
DSP56303 User's Manual
Description
WDS0
Mode
0
0
8-Bit Synchronous Data (shift register mode)
1
1
Reserved
0
2
10-Bit Asynchronous (1 start, 8 data, 1 stop)
1
3
Reserved
0
4
11-Bit Asynchronous
(1 start, 8 data, 1 even parity, 1 stop)
1
5
11-Bit Asynchronous
(1 start, 8 data, 1 odd parity, 1 stop)
0
6
11-Bit Multidrop Asynchronous
(1 start, 8 data, 1 data type, 1 stop)
1
7
Reserved
Word Formats
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