B-2 Operating Mode Register (Omr) - Motorola DSP56303 User Manual

Application:
Central Processor
External Bus Disable
Stop Delay
Memory Switch Mode
Core-DMA Priority
CDP(1:0) Core-DMA Priority
00 Core vs DMA Priority
01 DMA accesses > Core
10 DMA accesses = Core
11 DMA accesses < Core
Burst Mode Enable
TA Synchronize Select
Bus Release Timing
Asynchronous Bus Arbitration Enable
Address Attribute Priority Disable
Address Trace Enable
Stack Extension XY Select
Extended Stack Underflow Flag
Extended Stack Overflow Flag
Extended Stack Wrap Flag
Stack Extension Enable
23 22 21 20 19 18 17 16
* * * SEN WRP EOV EUN XYS
0 0 0
System Stack Control
Status Register (SCS)
Operating Mode Register (OMR) Read/Write
Reset = $00030X; X = latched from levels on Mode pins
Figure B-2. Operating Mode Register (OMR)
MOD(D:A) Mode Reset Vector
0000 0
0001 1
0010 2
0011 3
0100 4
0101 5
0110 6
0111 7
1000 8
1001 9
1010 A
1011 B
1100 C
1101 D
1110 E
1111 F
15 14 13 12 11 10 9
APD ABE XYS BRT TAS BE CDP1 CDP0
Extended Chip Operating
Mode Register (EOM)
Programming Reference
Programming Sheets
Date:
Programmer:
Chip Operating Modes
Description
$C00000 Expanded mode
$FF0000 Bootstrap from byte-wide memory
$FF0000 Bootstrap through SCI
— Reserved
$FF0000 Bootstrap from ISA host
$FF0000 Bootstrap from HC11 host
$FF0000 Bootstrap from 8051 host
$FF0000 Bootstrap from MC68302 host
$008000 Expanded mode
$FF0000 Bootstrap from byte-wide memory
$FF0000 Bootstrap through SCI
$FF0000 Bootstrap through SCI
$FF0000 Bootstrap from ISA host
$FF0000 Bootstrap from HC11 host
$FF0000 Bootstrap from 8051 host
$FF0000 Bootstrap from MC68302 host
8 7 6 5 4 3
MS SD * EBD MD MC
0
Chip Operating Mode
Register (COM)
*
= Reserved, Program as 0
Sheet 2 of 2
2 1 0
MB MA
B-13