Dram Control Register (Dcr) - Motorola DSP56303 User Manual

Table 4-8. Bus Control Register (BCR) Bit Definitions (Continued)
Bit
Bit Name Reset Value
Number
9–5 BA1W[4–0]
4–0 BA0W[4–0]
4.6.2

DRAM Control Register (DCR)

The DRAM controller is an efficient interface to dynamic RAM devices in both random
read/write cycles and Fast Access mode (Page mode). An on-chip DRAM controller controls
the page hit circuit, the address multiplexing (row address and column address), the control
signal generation (
CAS
variety of DRAM module sizes and access times. The on-chip DRAM controller
configuration is determined by the DRAM Control Register (DCR). The DRAM Control
Register (DCR) is a 24-bit read/write register that controls and configures the external DRAM
accesses. The DCR bits are shown in Figure 4-7.
Note: To prevent improper device operation, you must guarantee that all the DCR bits
except BSTR are not changed during a DRAM access.
11111 Bus Area 1 Wait State Control
(31 wait Defines the number of wait states (one through 31) inserted into each external
states) SRAM access to Area 1 (DRAM accesses are not affected by these bits). Area 1 is
the area defined by AAR1.
NOTE: Do not program the value of these bits as zero, since SRAM memory
access requires at least one wait state.
When four through seven wait states are selected, one additional wait state is
inserted at the end of the access. When selecting eight or more wait states, two
additional wait states are inserted at the end of the access. These trailing wait
states increase the data hold time and the memory release time and do not
increase the memory access time.
11111 Bus Area 0 Wait State Control
(31 wait Defines the number of wait states (one through 31) inserted in each external
states) SRAM access to Area 0 (DRAM accesses are not affected by these bits). Area 0 is
the area defined by AAR0.
NOTE: Do not program the value of these bits as zero, since SRAM memory
access requires at least one wait state.
When selecting four through seven wait states, one additional wait state is inserted
at the end of the access. When selecting eight or more wait states, two additional
wait states are inserted at the end of the access. These trailing wait states increase
the data hold time and the memory release time and do not increase the memory
access time.
and ) and the refresh access generation (
RAS
Core Configuration
Bus Interface Unit (BIU) Registers
Description
before
CAS
) for a
RAS
4-27