Motorola DSP56303 User Manual page 38

External Memory Expansion Port (Port A)
Table 2-8. External Bus Control Signals (Continued)
Signal
Type
Name
BB Input/ Input
Output
CAS Output Tri-stated
BCLK Output Tri-stated
BCLK Output Tri-stated
2-8
State During Reset,
Stop, or Wait
Bus Busy—Indicates that the bus is active and must be asserted and
deasserted synchronous to CLKOUT. Only after BB is deasserted can
the pending bus master become the bus master (and then assert the
signal again). The bus master can keep BB asserted after ceasing bus
activity, regardless of whether BR is asserted or deasserted. This is
called "bus parking" and allows the current bus master to reuse the
bus without re-arbitration until another device requires the bus. BB is
deasserted by an "active pull-up" method (that is, BB is driven high
and then released and held high by an external pull-up resistor).
BB requires an external pull-up resistor.
Column Address Strobe—When the DSP is the bus master, DRAM
uses CAS to strobe the column address. Otherwise, if the Bus
Mastership Enable (BME) bit in the DRAM Control Register is cleared,
the signal is tri-stated.
Bus Clock—When the DSP is the bus master, BCLK is active when
the OMR[ATE] is set. When BCLK is active and synchronized to
CLKOUT by the internal PLL, BCLK precedes CLKOUT by one-fourth
of a clock cycle.
Bus Clock Not—When the DSP is the bus master, BCLK is the
inverse of the BCLK signal. Otherwise, the signal is tri-stated.
DSP56303 User's Manual
Signal Description