Interface Status Register (Isr) Bit Definitions - Motorola DSP56303 User Manual

Host Programmer Model
Table 6-17. Interface Status Register (ISR) Bit Definitions
Bit Number Bit Name
7 HREQ
6–5
4 HF3
3 HF2
2 TRDY
6-28
Reset Value
0 (Hardware Host Request
and Software If HDRQ is set, the HREQ bit indicates the status of the external transmit
reset) and receive request output signals (HTRQ and HRRQ). If HDRQ is
1 (Individual cleared, HREQ indicates the status of the external host request output
reset and signal (HREQ). The HREQ bit is set from either or both of two conditions—
TREQ is set) the receive byte registers are full or the transmit byte registers are empty.
1 (Stop reset These conditions are indicated by status bits: ISR RXDF indicates that the
and TREQ is receive byte registers are full, and ISR TXDE indicates that the transmit
set) byte registers are empty. If the interrupt source is enabled by the
associated request enable bit in the ICR, HREQ is set if one or more of the
two enabled interrupt sources is set.
HDRQ
0
0
1
1
0 Reserved. Write to 0 for future compatibility.
0 Host Flag 3
Indicates the state of HF3 in the HCR on the DSP side. HF3 can be
changed only by the DSP56303. Hardware and software reset clear HF3.
0 Host Flag 2
Indicates the state of HF2 in the HCR on the DSP side. HF2 can be
changed only by the DSP56303. Hardware and software reset clear HF2.
1 Transmitter Ready
Indicates that TXH:TXM:TXL and the HRX registers are empty. If TRDY is
set, the data that the host processor writes to TXH:TXM:TXL is
immediately transferred to the DSP side of the HI08. This feature has
many applications. For example, if the host processor issues a host
command that causes the DSP56303 to read the HRX, the host processor
can be guaranteed that the data it just transferred to the HI08 is that being
received by the DSP56303. Hardware, software, individual, and stop
resets all set TRDY.
DSP56303 User's Manual
Description
HREQ
0 HREQ is cleared; no host processor
interrupts are requested.
1 HREQ is set; an interrupt is requested.
0 HTRQ and HRRQ are cleared, no host
processor interrupts are requested.
1 HTRQ or HRRQ are set; an interrupt is
requested.
CAUTION:
TRDY = TXDE and HRDF
Effect