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Application:
ESSI
Receive Exception Interrupt Enable
0 = Disable
1 = Enable
Transmit Exception Interrupt Enable
0 = Disable
1 = Enable
Receive Last Slot Interrupt Enable
0 = Disable
1 = Enable
Transmit Last Slot Interrupt Enable
0 = Disable
1 = Enable
Receive Interrupt Enable
0 = Disable
1 = Enable
Transmit Interrupt Enable
0 = Disable
1 = Enable
Receiver Enable
0 = Disable
1 = Enable
Transmit 0 Enable
0 = Disable
Transmit 1 Enable (SYN=1 only)
0 = Disable
Transmit 2 Enable (SYN=1 only)
0 = Disable
Mode Select
0 = Normal
Sync/Async Control
(Tx & Rx transfer together or not)
0 = Asynchronous
1 = Synchronous
23 22 21 20
19 18 17 16
REIE
TEIE
RLIE
TLIE
RIE
TIE
ESSI Control Register B (CRBx)
Reset = $000000
Figure B-16. ESSI Control Register B (CRB)
1 = Enable
1 = Enable
1 = Enable
1 = Network
15 14 13 12 11 10 9
RE
TE0
TE1 TE2 MOD SYN CKP
ESSI0—X:$FFFFB6 Read/Write
ESSI1—X:$FFFFA6 Read/Write
Programming Reference
Date:
Programmer:
Clock Polarity
(clk edge data & Frame Sync clocked out/in)
0 = out on rising/in on falling
1 = in on rising/out on falling
Frame Sync Polarity
0 = high level (positive)
1 = low level (negative)
Frame Sync Relative Timing
(WL Frame Sync only)
0 = with first data bit
1 = 1 clock cycle earlier than first data bit
Frame Sync
Length
FSL1
FSL0
TX
0
0
Word
0
1
Bit
1
0
Bit
1
1
Word
Shift Direction
0 = MSB First
Clock Source Direction
0 = External Clock
Serial Control Direction Bits (see Table 7-2)
Pin
SC0
Rx Clk
SC1
Rx Frame Sync
SC2
Tx Frame Sync
8
7
6
FSP FSR FSL1
FSL0
SHFD
SCKD SCD2 SCD1 SCD0 OF1 OF0
Programming Sheets
Sheet 2 of 3
RX
Word
Word
Bit
Bit
1 = LSB First
1 = Internal Clock
SCDx = 0 (Input)
SCDx = 1 (Output)
Flag 0
Flag 1
Tx, Rx Frame Sync
Output Flag x
If SYN = 1 and SCD1 = 1
OFx
SCx Pin
5
4
3
2
1
0
B-27
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