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3.3.3
External I/O Space—Y Data Memory
The off-chip peripheral registers should be mapped into the top 128 locations of Y data
memory ($FFFF80–$FFFFFF in the 24-bit Address mode or $FF80–$FFFF in the 16-bit
Address mode) to take advantage of the Move Peripheral Data (MOVEP) instruction and the
bit-oriented instructions (BCHG, BCLR, BSET, BTST, BRCLR, BRSET, BSCLR, BSSET,
JCLR, JSET, JSCLR, and JSSET).
3.4
Dynamic Memory Configuration Switching
Do not change the OMR[MS] bit when the SR[CE] bit is set. The Instruction Cache occupies
the top 1 K of what is otherwise Program RAM, and to switch memory into or out of Program
RAM when the cache is enabled can cause conflicts. To change the MS bit when CE is set:
1. Clear CE.
2. Change MS.
3. Set CE.
To ensure that dynamic switching is trouble-free, do not allow any
accesses (including instruction fetches) to or from the affected address
ranges in program and data memories during the switch cycle.
Because an interrupt could cause the DSP to fetch instructions out of sequence and might
violate the switch condition, special care should be taken in relation to the interrupt vector
routines.
Pay special attention when executing a memory switch routine using the
OnCE port. Running the switch routine in trace mode, for example, can
cause the switch to complete after the MS/MSW bits change while the DSP
is in Debug mode. As a result, subsequent instructions may be fetched
according to the new memory configuration (after the switch) and thus
may execute improperly.
Dynamic Memory Configuration Switching
CAUTION
CAUTION
Memory Configuration
3-5
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