Bus Control Register (Bcr) Bit Definitions - Motorola DSP56303 User Manual

Bus Interface Unit (BIU) Registers
Table 4-8. Bus Control Register (BCR) Bit Definitions
Bit
Bit Name Reset Value
Number
23 BRH
22 BLH
21 BBS
20–16 BDFW[4–0]
15–13 BA3W[2–0]
(7 wait states)
12–10 BA2W[2–0]
(7 wait states)
4-26
0 Bus Request Hold
Asserts the BR signal, even if no external access is needed. When BRH is set, the
BR signal is always asserted. If BRH is cleared, the BR is asserted only if an
external access is attempted or pending.
0 Bus Lock Hold
Asserts the BL signal, even if no read-modify-write access is occurring. When BLH
is set, the BL signal is always asserted. If BLH is cleared, the BL signal is asserted
only if a read-modify-write external access is attempted.
0 Bus State
This read-only bit is set when the DSP is the bus master and is cleared otherwise.
11111 Bus Default Area Wait State Control
(31 wait Defines the number of wait states (one through 31) inserted into each external
states) access to an area that is not defined by any of the AAR registers. The access type
for this area is SRAM only. These bits should not be programmed as zero since
SRAM memory access requires at least one wait state.
When four through seven wait states are selected, one additional wait state is
inserted at the end of the access. When selecting eight or more wait states, two
additional wait states are inserted at the end of the access. These trailing wait
states increase the data hold time and the memory release time and do not
increase the memory access time.
1 Bus Area 3 Wait State Control
Defines the number of wait states (one through seven) inserted in each external
SRAM access to Area 3 (DRAM accesses are not affected by these bits). Area 3 is
the area defined by AAR3.
NOTE: Do not program the value of these bits as zero since SRAM memory
access requires at least one wait state.
When four through seven wait states are selected, one additional wait state is
inserted at the end of the access. This trailing wait state increases the data hold
time and the memory release time and does not increase the memory access time.
111 Bus Area 2 Wait State Control
Defines the number of wait states (one through seven) inserted into each external
SRAM access to Area 2 (DRAM accesses are not affected by these bits). Area 2 is
the area defined by AAR2.
NOTE: Do not program the value of these bits as zero, since SRAM memory
access requires at least one wait state.
When four through seven wait states are selected, one additional wait state is
inserted at the end of the access. This trailing wait state increases the data hold
time and the memory release time and does not increase the memory access time.
DSP56303 User's Manual
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