Motorola DSP56303 User Manual page 15

Tables
1-1 High True/Low True Signal Conventions ................................................................. 1-2
1-2 On-Chip Memory....................................................................................................... 1-9
2-1 DSP56303 Functional Signal Groupings ................................................................... 2-1
2-2 Power Inputs .............................................................................................................. 2-3
2-3 Grounds...................................................................................................................... 2-4
2-4 Clock Signals ............................................................................................................. 2-5
2-5 Phase Lock Loop Signals........................................................................................... 2-5
2-6 External Address Bus Signals.................................................................................... 2-6
2-7 External Data Bus Signals ......................................................................................... 2-6
2-8 External Bus Control Signals..................................................................................... 2-6
2-9 Interrupt and Mode Control ....................................................................................... 2-9
2-10 Host Port Usage Considerations .............................................................................. 2-10
2-11 Host Interface........................................................................................................... 2-11
2-12 Enhanced Synchronous Serial Interface 0 (ESSI0) ................................................. 2-15
2-13 Enhanced Synchronous Serial Interface 1 (ESSI1) ................................................. 2-17
2-14 Serial Communication Interface (SCI) .................................................................... 2-19
2-15 Triple Timer Signals ................................................................................................ 2-20
2-16 JTAG/OnCE Interface ............................................................................................. 2-21
3-1 DSP56303 RAM Configurations ............................................................................... 3-6
3-2 DSP56303 RAM Address Ranges by Configuration................................................. 3-6
4-1 DSP56303 Operating Modes ..................................................................................... 4-2
4-2 Status Register Bit Definitions ................................................................................ 4-10
4-3 Operating Mode Register (OMR) Bit Definitions ................................................... 4-15
4-4 Interrupt Priority Level Bits..................................................................................... 4-20
4-5 Interrupt Sources...................................................................................................... 4-20
4-6 Interrupt Source Priorities Within an IPL................................................................ 4-22
4-7 PLL Control Register (PCTL) Bit Definitions ........................................................ 4-24
4-8 Bus Control Register (BCR) Bit Definitions ........................................................... 4-26
4-9 DRAM Control Register (DCR) Bit Definitions ..................................................... 4-28
4-10 Address Attribute Registers (AAR[0-3]) Bit Definitions ....................................... 4-30
4-11 DMA Control Register (DCR) Bit Definitions....................................................... 4-32
5-1 DMA-Accessible Registers........................................................................................ 5-5
6-1 HI08 Signal Definitions for Operational Modes........................................................ 6-3
6-2 HI08 Data Strobe Signals .......................................................................................... 6-4
6-3 HI08 Host Request Signals ........................................................................................ 6-4
6-4 DMA Request Sources............................................................................................... 6-9
6-5 HREQ Pin Operation In Single Request Mode (ICR[2]=HDRQ=0)....................... 6-10
6-6 HTRQ and HRRQ Pin Operation In Double Request Mode (ICR[2]=HDRQ=1) .. 6-10
6-7 HI08 Boot Modes..................................................................................................... 6-12
6-8 Host Control Register (HCR) Bit Definitions.......................................................... 6-14
6-9 Host Status Register (HSR) Bit Definitions ............................................................ 6-15
6-10 HDR and HDDR Functionality................................................................................ 6-16
6-11 Host Base Address Register (HBAR) Bit Definitions ............................................. 6-17
Tables
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