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4.6.2 DRAM Control Register (DCR) .......................................................................................... 4-27
4.6.3 Address Attribute Registers (AAR[0-3]) ............................................................................ 4-30
4.7
DMA Control Registers 5-0 (DCR[5-0]) ........................................................................... 4-32
4.8
Device Identification Register (IDR)................................................................................... 4-37
4.9
JTAG Identification (ID) Register ....................................................................................... 4-38
4.10
JTAG Boundary Scan Register (BSR)................................................................................. 4-38
5
Chapter
5.1
Peripheral Initialization Steps ................................................................................................ 5-1
5.2
Mapping the Control Registers .............................................................................................. 5-2
5.3
Reading Status Registers ....................................................................................................... 5-2
5.4
Data Transfer Methods .......................................................................................................... 5-3
5.4.1 Polling.................................................................................................................................... 5-3
5.4.2 Interrupts ................................................................................................................................ 5-3
5.4.3 DMA ...................................................................................................................................... 5-5
5.4.4 Advantages and Disadvantages ............................................................................................. 5-6
5.5
General-Purpose Input/Output (GPIO) .................................................................................. 5-6
5.5.1 Port B Signals and Registers.................................................................................................. 5-7
5.5.2 Port C Signals and Registers.................................................................................................. 5-8
5.5.3 Port D Signals and Registers ................................................................................................. 5-8
5.5.4 Port E Signals and Registers .................................................................................................. 5-9
5.5.5 Triple Timer Signals and Registers ....................................................................................... 5-9
6
Chapter
6.1
Features .................................................................................................................................. 6-1
6.1.1 DSP Core Interface ................................................................................................................ 6-1
6.1.2 Host Processor Interface ........................................................................................................ 6-2
6.2
Host Port Signals ................................................................................................................... 6-3
6.3
Overview................................................................................................................................ 6-4
6.4
Operation ............................................................................................................................... 6-6
6.4.1 Software Polling .................................................................................................................... 6-7
6.4.2 Core Interrupts and Host Commands..................................................................................... 6-7
6.4.3 Core DMA Access ................................................................................................................. 6-9
6.4.4 Host Requests ........................................................................................................................ 6-9
6.4.5 Endian Modes ...................................................................................................................... 6-11
6.5
Boot-up Using the HI08 Host Port ...................................................................................... 6-12
6.6
DSP Core Programming Model ........................................................................................... 6-13
6.6.1 Host Control Register (HCR) .............................................................................................. 6-14
6.6.2 Host Status Register (HSR) ................................................................................................. 6-15
6.6.3 Host Data Direction Register (HDDR) ................................................................................ 6-16
6.6.4 Host Data Register (HDR) ................................................................................................... 6-16
6.6.5 Host Base Address Register (HBAR) .................................................................................. 6-17
Contents
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