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2.12
JTAG/OnCE Interface
Signal Name
Type
TCK
Input
TDI
Input
TDO
Output
TMS
Input
TRST
Input
DE
Input/Output
Table 2-16. JTAG/OnCE Interface
State During
Reset
Input
Test Clock—A test clock signal for synchronizing JTAG test
logic.
This input is 5 V tolerant.
Input
Test Data Input—A test data serial signal for test instructions
and data. TDI is sampled on the rising edge of TCK and has an
internal pull-up resistor.
This input is 5 V tolerant.
Tri-stated
Test Data Output—A test data serial signal for test
instructions and data. TDO can be tri-stated. The signal is
actively driven in the shift-IR and shift-DR controller states and
changes on the falling edge of TCK.
This pin is 5 V tolerant.
Input
Test Mode Select—Sequences the test controller's state
machine, is sampled on the rising edge of TCK, and has an
internal pull-up resistor.
This input is 5 V tolerant.
Input
Test Reset—Asynchronously initializes the test controller, has
an internal pull-up resistor, and must be asserted after power
up.
This input is 5 V tolerant.
Input
Debug Event—Provides a way to enter Debug mode from an
external command controller (as input) or to acknowledge that
the chip has entered Debug mode (as output). When asserted
as an input, DE causes the DSP56300 core to finish the current
instruction, save the instruction pipeline information, enter
Debug mode, and wait for commands from the debug serial
input line. When a debug request or a breakpoint condition
cause the chip to enter Debug mode DE is asserted as an
output for three clock cycles. DE has an internal pull-up
resistor.
DE is not a standard part of the JTAG Test Access Port (TAP)
Controller. It connects to the OnCE module to initiate Debug
mode directly or to provide a direct external indication that the
chip has entered the Debug mode. All other interface with the
OnCE module must occur through the JTAG port.
This input is 5 V tolerant.
Signals/Connections
JTAG/OnCE Interface
Signal Description
2-21
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