Mapping The Control Registers; Reading Status Registers; Memory Mapping Of Peripherals Control Registers - Motorola DSP56303 User Manual

Mapping the Control Registers

5.2 Mapping the Control Registers
The I/O peripherals are controlled through registers mapped to the top 128 words of X-data
memory ($FFFF80–$FFFFFF). Referred to as the internal I/O space, the control registers are
accessed by move (MOVE, MOVEP) instructions and bit-oriented instructions (BCHG,
BCLR, BSET, BTST, BRCLR, BRSET, BSCLR, BSSET, JCLR, JSET, JSCLR, and JSSET).
The contents of the internal X I/O memory space are listed in Appendix B, Programming
Reference, Table B-2.
$FFFFFF
$FFFF80
$FFF000
$FF0000
$000800
$000000
Figure 5-1. Memory Mapping of Peripherals Control Registers
5.3

Reading Status Registers

Each peripheral has a read-only status register that indicate the state of the peripheral at a
given time. The HI08, ESSI, and SCI have dedicated status registers. The triple timer has
status bits embedded within a control/status register. Changes in the status bits can generate
interrupt conditions. For example, the HI08 has a host status register with two host flag bits
that can be encoded by the host to generate an interrupt in the DSP.
5-2
X-Data Memory
Internal I/O
External
Internal
Reserved
External
Internal
X-Data RAM
2 K (default)
DSP56303 User's Manual
Peripherals Control Registers
Memory Space