Bit Space With Instruction Cache Enabled (1, 0, 1) - Motorola DSP56303 User Manual

24-bit digital signal processor
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Memory Maps
Program
$FFFF
External
$0C00
Internal
Program RAM
$0000
Bit Settings
SC
MS
CE
1
0
1
Figure 3-6. 16-bit Space with Instruction Cache Enabled (1, 0, 1)
3-12
$FFFF
Internal I/O
$FF80
$0800
X data RAM
3 K
$0000
Program RAM
X Data RAM
3 K
2 K
$000–$BFF
$000–$7FF
DSP56303 User's Manual
X Data
$FFFF
$FF80
External
$0800
Internal
2 K
$0000
Memory Configuration
Y Data RAM
2 K
$000–$7FF
Y Data
External I/O
External
Internal
Y data RAM
2 K
Addressable
Cache
Memory Size
1 K
64 K
internal not
accessible

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