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Central Processor Unit (CPU) Registers
example, MOVEC). Parallel move operations affect only the S and L bits of the CCR.
During processor reset, all CCR bits are cleared.
n
The definition of the three 8-bit registers within the SR is primarily for the purpose of
compatibility with other Motorola DSPs. Bit definitions in the following paragraphs
identify the bits within the SR and not within the subregister.
Extended Mode Register (EMR)
23 22
21 20
19 18
CP[1–0] RM SM CE
Reset:
1
1
0
0
0
Reserved bit. Read as zero; write to zero for future compatibility
Bit Number
Bit Name
23–22
CP[1–0]
21
RM
20
SM
4-10
Mode Register (MR)
17 16
15 14
13 12
SA FV LF DM SC
0
0
0
0
0
0
Figure 4-1. Status Register (SR)
Table 4-2. Status Register Bit Definitions
Reset Value
11
Core Priority
Under control of the CDP[1–0] bits in the OMR, the CP bits specify the
priority of core accesses to external memory. These bits are compared
against the priority bits of the active DMA channel. If the core priority is
greater than the DMA priority, the DMA waits for a free time slot on the
external bus. If the core priority is less than the DMA priority, the core waits
for a free time slot on the external bus. If the core priority equals the DMA
priority, the core and DMA access the external bus in a round robin pattern
(for example, ... P, X, Y, DMA, P, X, Y, ...).
Priority
Mode
Dynamic
Static
0
Rounding Mode
Selects the type of rounding performed by the Data ALU during arithmetic
operations. If RM is cleared, convergent rounding is selected. If RM is set,
two's-complement rounding is selected.
0
Arithmetic Saturation Mode
Selects automatic saturation on 48 bits for the results going to the
accumulator. This saturation is performed by a special circuit inside the
MAC unit. The purpose of this bit is to provide an Arithmetic Saturation
mode for algorithms that do not recognize or cannot take advantage of the
extension accumulator.
DSP56303 User's Manual
Condition Code Register (CCR)
11 10
9
8
7
S[1–0]
I[1–0]
S
0
0
0
1
1
0
Description
Core
DMA
Priority
Priority
0
Determined
(Lowest)
by DCRn
1
(DPR[1–0])
2
for active
DMA
3
channel
(Highest)
core < DMA
core = DMA
core > DMA
6
5
4
3
2
L
E
U
N
Z
0
0
0
0
0
OMR
SR (CP[1–0])
(CDP[1-0])
00
00
00
01
00
10
00
11
01
xx
10
xx
11
xx
1
0
V
C
0
0
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