Motorola DSP56303 User Manual page 72

24-bit digital signal processor
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Operating Modes
Table 4-1. DSP56303 Operating Modes (Continued)
Mode
MODD
MODC
A
1
0
B
1
0
C
1
1
4-6
Reset
MODB
MODA
Vector
1
0
$FF0000
1
1
$FF0000
0
0
$FF0000
DSP56303 User's Manual
Description
Bootstrap through SCI
The DSP is configured to load the program RAM
from the SCI interface. The number of program
words to be loaded and the starting address must be
specified. The SCI bootstrap code expects to receive
3 bytes specifying the number of program words, 3
bytes specifying the address to start loading the
program words and then 3 bytes for each program
word to be loaded. The number of words, the starting
address and the program words are received least
significant byte first followed by the mid and then by
the most significant byte. After receiving the program
words, program execution starts in the same address
where loading started. The SCI is programmed to
work in asynchronous mode with 8 data bits, 1 stop
bit and no parity. The clock source is external and
the clock frequency must be 16x the baud rate. After
each byte is received, it is echoed back through the
SCI transmitter.
Reserved
HI08 bootstrap in ISA/DSP563xx mode
The HI08 is configured to load the program RAM
from the Host Interface programmed to operate in
the ISA mode. The HOST ISA bootstrap code
expects to read a 24-bit word specifying the number
of program words, a 24-bit word specifying the
address to start loading the program words and then
a 24-bit word for each program word to be loaded.
The program words are stored in contiguous P RAM
memory locations starting at the specified starting
address. After reading the program words, program
execution starts from the same address where
loading started. The Host Interface bootstrap load
program may be stopped by setting the Host Flag 0
(HF0). This starts execution of the loaded program
from the specified starting address.

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