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Bus X Data Memory Enable (BXEN) bit 4-31
Bus Y Data Memory Enable (BYEN) bit 4-31
C
Cache Burst Mode Enable (BE) bit 4-17
Cache Enable (CE) bit 4-10
Carry (C) bit 4-14
Central Processing Unit (CPU) 1-1
Chip Operating Mode (MD–MA) bits 4-18
chip-select
logic 6-17
signal 6-4
Clock 2-5
Clock Divider (CD) bits 8-20
,
clock generator 7-11
7-17
Clock Generator (CLKGEN) 1-8
Clock Out Divider (COD) 8-19
Clock Output Disable (COD) bit 4-24
Clock Polarity (CKP) bit 7-22
Clock Prescaler (SCP) 8-19
Clock Source Direction (SCKD) bit 7-22
CMOS 1-5
,
,
codec 7-4
7-10
7-13
COM byte 4-15
Command Vector Register (CVR) 6-23
Host Command (HC) 6-27
Host Vector (HV) 6-27
programming sheet B-24
Condition Code Register (CCR) 4-10
Carry (C) 4-14
Extension (E) 4-14
Limit (L) 4-14
Negative (N) 4-14
Overflow (V) 4-14
Scaling (S) 4-13
Unnormalized (U) 4-14
Zero (Z) 4-14
Control Register A (CRA)
Alignment Control (ALC) 7-16
Frame Rate Divider Control (DC) 7-16
Prescale Modulus Select (PM) 7-16
Prescaler Range (PSR) 7-16
programming sheet B-26
Select SCK (SSC1) 7-15
Word Length Control (WL) 7-15
Control Register B (CRB)
Clock Polarity (CKP) 7-22
Clock Source Direction (SCKD) 7-22
Frame Sync Length (FSL) 7-22
Frame Sync Polarity (FSP) 7-22
Frame Sync Relative Timing (FSR) 7-22
Mode Select (MOD) 7-21
programming sheet B-27
Index-2
,
4-11
,
6-26
DSP56303 User's Manual
Receive Enable (RE) 7-20
Receive Exception Interrupt Enable (REIE) 7-19
Receive Interrupt Enable (RIE) 7-19
Receive Last Slot Interrupt Enable (RLIE) 7-19
Serial Control Direction 0 (SCD0) 7-23
Serial Control Direction 1 (SCD1) 7-23
Serial Control Direction 2 (SCD2) 7-23
Serial Output Flag 0 (OF0) 7-23
Serial Output Flag 1 (OF1) 7-23
Shift Directions (SHFD) 7-22
Synchronous/Asynchronous (SYN) 7-21
Transmit 0 Enable (TE0) 7-20
Transmit 1 Enable (TE1) 7-21
Transmit 2 Enable (TE2) 7-21
Transmit Exception Interrupt Enable (TEIE) 7-19
Transmit Interrupt Enable (TIE) 7-20
Transmit Last Slot Interrupt Enable (TLIE) 7-19
Core Priority (CP) bits 4-10
Core-DMA Priority (CDP) bits 4-17
crystal frequency 8-6
Crystal Range (XTLR) bit 4-24
D
data and control host processor registers 6-13
Data Arithmetic Logic Unit (Data ALU) 1-6
Data Input (DI) bit 9-29
data memory expansion 1-10
Data Output (DO) bit 9-29
data strobe 6-4
data transfer methods 5-3
Debug support 1-5
Direct Memory Access (DMA) 6-6
Request Source bits 4-32
transfers and host bus 6-9
triggered by timer 9-25
Direction (DIR) bit 9-30
Division Factor (DF) bits 4-25
DMA Address Mode (DAM) bit 4-36
DMA Channel Enable (DE) bit 4-32
DMA Channel Priority (DPR) bit 4-34
DMA Continuous Mode Enable (DCON) bit 4-35
DMA Control Registers (DCR5–DCR0)
programming sheet B-20
DMA Control Registers (DCRs) 4-32
bit definitions 4-32
DMA Address Mode (DAM) 4-36
DMA Channel Enable (DE) 4-32
DMA Channel Priority (DPR) 4-34
DMA Continuous Mode Enable (DCON) 4-35
DMA Destination Space (DDS) 4-37
DMA Interrupt Enable (DIE) 4-33
DMA Request Source (DRS) 4-36
DMA Source Space (DSS) 4-37
,
6-9
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