Figure 4-3 Dsp56309 Operating Mode Register (Omr); Operating Mode Register (Omr) - Motorola DSP56309 User Manual

DMA Request Source Bits
DRS4... DRS0
10101Ð11111
4.6

OPERATING MODE REGISTER (OMR)

The OMR is a 24-bit, read/write register divided into three byte-sized units. The first
two bytes (COM and EOM) control the chipÕs operating mode. The third byte (SCS)
controls and monitors the stack extension. The OMR control bits are shown in
Figure 4-3. Refer to the DSP56300
SCS
23 22 21 20 19
PEN SEN WRP EOV EUN XYS ATE APD ABE BRT TAS BE
PENÑPatch Enable
SENÑStack Extension Enable
WRPÑExtended Stack Wrap Flag
EOVÑExtended Stack Overflow Flag
EUNÑExtended Stack Underflow Flag
XYSÑStack Extension Space Select
- Reserved bit. Read as zero, should be written with zero for future compatibility.

Figure 4-3 DSP56309 Operating Mode Register (OMR)

MOTOROLA
Table 4-5 DMA Request Sources (Continued)
01101
01110
01111
10000
10001
10010
10011
10100
Family Manual
18 17 16 15 14 13
ATEÑAddress Tracing Enable
APDÑAddress Priority Disable
ABEÑAsynch. Bus Arbitration Enable
BRTÑBus Release Timing
TASÑTA Synchronize Select
BEÑBurst Mode Enable
CDP1ÑCore-DMA Priority 1
CDP0ÑCore-DMA Priority 0
DSP56309UM/D
Operating Mode Register (OMR)
Requesting Device
ESSI1 Transmit Data (TDE1 = 1)
SCI Receive Data (RDRF = 1)
SCI Transmit Data (TDRE = 1)
Timer0 (TCF0 = 1)
Timer1 (TCF1 = 1)
Timer2 (TCF2 = 1)
Host Receive Data Full (HRDF = 1)
Host Transmit Data Empty (HTDE = 1)
Reserved
for a complete description of the OMR.
EOM
12 11 10 9 8
CDP1:0 MS SD
MSÑMemory Switch Mode
SDÑStop Delay
EBDÑExternal Bus Disable
MDÑOperating Mode D
MCÑOperating Mode C
MBÑOperating Mode B
MAÑOperating Mode A
Core Configuration
COM
7 6 5 4 3 2
EBD MD MC MB MA
1 0
4-17