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On-Chip Debug Unit
(3)
(4)
Pin configuration
and the N-Wire debug circuit is disabled. The first CPU instructions after
RESPOC can not be controlled by the debugger. The application software
must set OCDM.OCDM0 = 1 in order to enable the N-Wire interface and allow
debugger access to the on-chip debug unit.
During and after POC reset (OCDM.OCDM0 = 0) pins P05, P52...P55 are
configured as input ports.
External RESET
External reset by the RESET pin sets OCDM.OCDM0 = 1, i.e. the pins are
defined as N-Wire interface pins. If connected the debugger can communicate
with the on-chip debug unit and take over CPU control.
During and after RESET the pins P05, P52...P55 are configured as follows:
• DRST, DDI, DCK, DMS are inputs.
• DDO is output, but in high impedance state as long as DRST = 0.
Other resets
Resets from all other reset sources do not affect the pins P05, P52...P55.
An internal pull-down resistor is provided for the pin P05/DRST. During and
after any reset the resistor is connected to P05/DRST, ensuring that the
N-Wire interface is kept in reset state, if no debugger is connected. The
internal pull-down resistor is connected by reset from any source and can be
disconnected via OCDM.OCDM0.
The DRST signal depicts the N-Wire interface reset signal. If DRST = 0 the
on-chip debug unit is kept in reset state and does not impact normal controller
operation. DRST is driven by the debugger, if one is connected. The debugger
may start communication with the controller by setting DRST = 1.
In N-Wire debug mode the configuration of the N-Wire interface pins can not
be changed by the pin configuration registers. The registers contents can be
changed but will have no effect on the pin configuration.
User's Manual U18743EE1V2UM00
Chapter 23
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