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Chapter 10
Note
Note
Note
364
1.
m = 0, 2
n = 1, 3
2.
The 32-bit capture in cascade free-running mode is not available for TAA4.
3.
Explanation of signals can be found in Figure 10-1 on page 307.
4.
Block diagrams of the input circuits can be found in Figure 10-2 on
page 308 to Figure 10-3 on page 308,
Figure 10-34 shows the block diagram of TAAm and TAAn in cascade mode.
Signals that are irrelevant in cascade mode are not shown, the connections to
the internal bus are also hidden for better readability of the image, as Figure
10-1 on page 307 can be used for a in-depth look of each timer.
Cascading of two TAA is only allowed for free-running mode with both capture/
compare registers set to capture mode. Proper operation of TAAm and TAAn is
not guaranteed for any other setting.
Figure 10-35 shows the recommended flow for setting up TAAm and TAAn in
cascade mode. As TAAm is used for general control, TAAn is set up first and
set in cascaded operation by setting the TAAnCSE bit to 1. Then TAAm is
initialized by selecting the proper clock setting and capture trigger input. Only
TIAAm0 and TIAAm1 can be used as external capture trigger.
When cascading TAAm and TAAn, set TAAnCSE=1 and TAAmCSE=0.
Operation starts when the count enable flag of TAAm (TAAmCE) is set to 1.
The counter of TAAm is used for the lower 16-bit of the 32-bit count value,
while the upper 16-bit are handled by TAAn.
Whenever the counter of TAAm overflows, the counter is cleared to 0, interrupt
INTTAAmOV is generated and the counter of TAAn is incremented by 1. When
the counter of TAAn overflows, the counter is also cleared to 0 and interrupt
INTTAAnOV is generated.
When a capture trigger 0/1 is detected by TAAm, a capture of the lower 16-bit
counter value to TAAmCCR0/1 and of the upper 16-bit counter value to
TAAnCCR0/1 at the same time. The interrupts of the TAAm will indicate the
capture (INTTAAmCC0/1).
Figure 10-36 on page 366 shows an example of a 32-bit capture timing.
User's Manual U18743EE1V2UM00
16-Bit Timer/Event Counter AA
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