Option Byte 0000 007B H - NEC V850ES/F 3-L Series User Manual

Chapter 4
4.3.2 Option byte 0000 007B
Address
Note
Table 4-22
Bit position Bit name
7 SUBCLK
4 LATENCY refer to "Flash Mask Options" on page 285
3 PLLO
2 PRSI
1 to 0 PLLI[1:0]
190
0000 007B .
H
7 6 5
SUBCLK 0 0
Bits marked with "0" must not be changed from their value "0".
Setting of option byte 0000 007B
Clock source in subclock operating mode:
0: SubOSC selection.
1: 240 KHz internal oscillator selection.
PLL output clock f and f
PLL
PLLO
0 (setting prohibited)
1
Divider Setting for peripheral clocks f
0: f , f = f
XP1 XP2 XX
1: f , f = f /2
XP1 XP2 XX
PLL input clock frequency selection:
PLLI1 PLLI0
0 0
0 1
1 x
User's Manual U18743EE1V2UM00
H
4 3 2
LATENCY PLLO PRSI
H
Function
selection:
XMPLL
f
XMPLL
f
PLLO
f /2
PLLO
and f
XP1 XP2
PLL input clock
Clock Generator
1 0
PLLI1 PLLI0
f
PLL
f
PLLO
f /2
PLLO
:
f = f
PLLI X
f = f /2
PLLI X
f = f /4
PLLI X