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16-Bit Timer/Event Counter AA
(8)
Address: TAA1OPT1 FFFFF5ADH, TAA3OPT1 FFFFF5CDH
Symbol
TAAn
TAAnOPT1
Note
Note
TAAnOPT1 - TAA option register 1
The TAAnOPT1 register is an 8-bit register used to set the 32-bit capture mode
by cascading two Timer AA.
This register can be read and written in 8-bit or 1-bit units.
RESET input clears this register to 00H.
7
6
5
0
0
CSE
n = 1, 3
TAAnCSE
0
16-bit non-cascaded mode
Set 32-bit cascaded capture mode. Timer AAn becomes the upper 16-
1
bit and slave. The master timer is TAAm with m = n - 1.
1.
When setting TAAnCSE, the timer becomes the upper 16-bit of a 32-bit
timer.
2.
If TAAnCSE = 1, TAAnCTL0.TAAnCE is forced to "0".
3.
Cascading is only available for capture with free-running counter.
4.
The following pairs of timers can be cascaded:
•
TAA0 and TAA1
(TAA0 will become master and will hold the lower 16-bit value)
•
TAA2 and TAA3
(TAA2 will become master and will hold the lower 16-bit value)
The table below shows the effects of the TAAnCSE flag on the timer operation:
Operating clock
macro clock from clock tree
Count Enable
TAAnCE bit of TAAnCTL0
Count Clock
selected by TAAnCKS[2:0]
TIAAn0 input with edge filter as
Capture Signal 0
selected by TAAnIS[1:0]
TIAAn1 input with edge filter as
Capture Signal 1
selected by TAAnIS[3:2]
Capture Interrupt INTTAAnCC0 or INTTAAnCC1
n=1 or 3; m= (n-1).
For details on the 32-bit capture mode, please refer to "32-bit Capture in Free-
Running Cascade Mode" on page 363.
User's Manual U18743EE1V2UM00
4
3
2
0
0
0
TAAnCCR1 register capture/compare selection
TAAnCSE=0
Chapter 10
1
<0>
R/W
0
0
R/W 00H
TAnCSE=1
macro clock of TAAm
TAAmCE bit of TAAm
Counter overflow from TAAm
TIAAm0 with edge filter
selected for TAAm
TIAAm1 with edge filter
selected for TAAm
INTTAAmCC0 or INTTAAmCC1
After
reset
325
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