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Chapter 17
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
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IIC shift register n (IICn)
The IICn register converts 8-bit serial data into 8-bit parallel data and vice
versa, and can be used for both transmission and reception.
Write and read operations to the IICn register are used to control the actual
transmit and receive operations.
Slave address register n (SVAn)
The SVAn register sets local addresses when in slave mode.
SO latch
The SO latch is used to retain the output level of the SDA0n pin.
Wakeup controller
This circuit generates an interrupt request when the address received by this
register matches the address value set to the SVAn register or when an
extension code is received.
Prescaler
This selects the sampling clock to be used.
Serial clock counter
This counter counts the serial clocks that are output and the serial clocks that
are input during transmit/receive operations and is used to verify that 8-bit data
was transmitted or received.
Interrupt request signal generator
This circuit controls the generation of interrupt request signals (INTIICn).
2
An I
C interrupt is generated following either of two triggers:
• Falling edge of eighth or ninth clock of the serial clock (set by IICCn.WTIMn
bit)
• Interrupt occurrence due to stop condition detection (set by IICCn.SPIEn bit)
Serial clock controller
In master mode, this circuit generates the clock output via the SCL0n pin from
the sampling clock.
Serial clock wait controller
This circuit controls the wait timing.
ACK output circuit, stop condition detector, start condition detector, and
ACK detector
These circuits are used to output and detect various control signals.
User's Manual U18743EE1V2UM00
2
I
C Bus (IIC)
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