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Clock Generator
4.2.4 Prescaler3 control registers
(1)
Access
Address
Initial Value
Table 4-16
Bit position
Bit name
4
BGCE0
1 to 0
BGCS0[1:0]
Note
(2)
Access
Address
Initial Value
These registers control the Prescaler3 that generates f
applied to the Watch Timer and the Clocked Serial Interface CSIB0. Prescaler3
includes a clock divider, a counter, and a comparator. For details see
"Operation of Prescaler3" on page 216.
PRSM0 - Prescaler3 mode register
The PRSM0 register controls the Prescaler3 operation.
This register can be read/written in 8-bit units.
FFFF F8B0
.
H
00
. This register is cleared by any reset.
H
7
6
5
0
0
0
R
R
R
PRSM0 register contents
Prescaler3 output:
Disabled.
0:
1: Enabled.
Selection of counter clock:
BGCS01
BGCS00
0
0
0
1
1
0
1
1
1.
Do not change the values of BGCS0[1:0] during Watch Timer operation.
2.
Set the BGCS0[1:0] bits before setting the BGCE0 bit to 1.
3.
Set the PRSM0 and PRSCM0 registers according to the main clock
frequency that is used to obtain an f
PRSCM0 - Prescaler3 compare register
The PRSCM0 register specifies the compare value and hence the output
frequency of f
.
BRG
This register can be read/written in 8-bit units.
FFFF F8B1
.
H
00
. This register is cleared by any reset.
H
7
6
5
PRSCM7 PRSCM6 PRSCM5 PRSCM4 PRSCM3 PRSCM2
R/W
R/W
R/W
User's Manual U18743EE1V2UM00
4
3
2
BGCE0
0
0
R/W
R
R
Function
Prescaler clock selection
frequency of 32,768 KHz.
BRG
4
3
2
R/W
R/W
R/W
Chapter 4
which can be
BRG
1
0
BGCS01
BGCS00
R/W
R/W
f
X
f
/2
X
f
/4
X
f
/8
X
1
0
PRSCM1
PRSCM0
R/W
R/W
183
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