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Clock Generator
(1)
HALT mode
X1 = ON, PLL = ON
Figure 4-3
Note
(2)
HALT mode
X1 = ON, PLL = ON
Figure 4-4
Note
Status transition from PLL operation
IDLE1 mode
X1 = ON, PLL = ON
Stand-by transition from PLL operation (PLL = ON)
1.
After the time set by the OSTS register has elapsed, the CPU returns to
the PLL mode.
2.
After the time set by the OSTS register has elapsed, the CPU returns to
the PLL mode. If the Watchdog Timer overflows (reset) while the oscillation
stabilization time is being counted, the CPU starts clock operation with the
internal oscillator.
Status transition from main clock-through operation (with PLL on)
X1 main clock-through mode
IDLE1 mode
X1 = ON, PLL = ON
Stand-by transition from x1 main clock-through operation (PLL = ON)
1.
After the time set by the OSTS register has elapsed, the CPU returns to
the through mode.
2.
After the time set by the OSTS register has elapsed, the CPU returns to
the through mode. If the Watchdog Timer overflows (reset) while the
oscillation stabilization time is counted, the CPU starts its clock operation
with the internal oscillator.
User's Manual U18743EE1V2UM00
PLL operation
(PLL = ON)
Note 1
IDLE2 mode
X1 = ON, PLL = OFF
(PLL = ON)
Note 1
IDLE2 mode
X1 = ON, PLL = OFF
Note 2
Software STOP mode
X1 = OFF, PLL = OFF
Note 2
Software STOP mode
X1 = OFF, PLL = OFF
Chapter 4
193
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