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Clock Generator
4.4.4 Available clocks in power save modes
Table 4-36
Operation status
Reset period
From reset release to
8 MHz internal oscillator setup
8 MHz
internal oscillator
Note1
MainOSC
Note1
release to setup
PLL/
Note1
release to setup
SubOSC
Note1
240 KHz
internal oscillator-
Note1
Sub
240 KHz
internal oscillator-
Security
Note1
The following table gives an overview of the clock signals available in the
various stand-by modes.
Clock operation in power save modes
f
/f
X
PLLI
Note2
Note2
x
x
Run
enable
HALT mode
enable
IDLE1 mode
enable
STOP mode
x
From STOP
release to
enable
oscillation
stabilization
Run
O
HALT mode
O
IDLE1 mode
O
IDLE2 mode
O
From IDLE2
O
STOP mode
x
From STOP
release to
O
oscillation
stabilization
Run
O
HALT mode
O
IDLE1 mode
O
IDLE2 mode
O
From IDLE2
O
STOP mode
x
From STOP
release to
O
oscillation
stabilization
Run
enable
IDLE mode
enable
Run
enable
HALT mode
enable
Run
-
HALT mode
-
User's Manual U18743EE1V2UM00
f
f
f
f
XT
RL
RH
PLL
f
Note2
Note2
PCL
O
x
x
x
O
O
O
x
O
O
enable
enable
O
O
enable
enable
O
O
enable
enable
O
x
x
enable
O
O
x
enable
O
enable enable enable
O
enable enable enable
O
enable enable enable
O
x
enable enable
O
x
enable enable
O
x
x
enable
O
x
enable enable
O
O
enable enable
O
O
enable enable
O
O
enable enable
O
x
enable enable
O
x
enable enable
O
x
x
enable
O
x
enable enable
O
enable enable enable enable enable
O
enable enable enable
O
O
enable enable enable enable
O
O
enable enable
O
O
-
enable
O
O
-
enable
f
f
f
f
XX
XP1
VBCLK
CPU
x
x
x
x
O
x
x
x
O
O
O
O
O
O
O
x
x
x
x
x
x
x
x
x
O
x
x
x
O
O
O
O
O
O
O
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
O
O
O
O
O
O
O
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
O
O
x
x
x
x
O
O
x
x
x
x
O
O
enable enable
O
x
enable enable
Chapter 4
f
f
XP2
XC
x
x
x
x
O
enable
O
enable
O
x
x
x
O
enable
O
O
O
O
O
x
x
x
x
x
x
x
x
x
O
O
O
O
O
x
x
x
x
x
x
x
x
x
enable enable
x
x
enable enable
x
x
enable enable
enable enable
211
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