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Clocked Serial Interface (CSIB)
Caution
1.
When transferring transmit data and receive data using DMA transfer, error
processing cannot be performed even if an overrun error occurs during
serial transfer. Check that the no overrun error has occurred by reading the
CBnSTR.CBnOVE bit after DMA transfer has been completed.
2.
In regards to registers that are forbidden from being rewritten during
operations (CBnCTL0.CBnPWR bit is 1), if rewriting has been carried out by
mistake during operations, set the CBnCTL0.CBnPWR bit to 0 once, then
initialize CSIBn. Registers to which rewriting during operation are prohibited
are shown below.
· CBnCTL0 register: CBnTXE, CBnRXE, CBnDIR, CBnTMS bit
· CBnCTL1 register: CBnCKP, CBnDAP, CBnCKS2-CBnCKS0 bit
· CBnCTL2 register: CBnCL3-CBnCL0 bit
3.
In the single transfer mode (CBnCTL0.CBnTMS bit = 0), when the
CBnCTL1.CBnDAP bit is set to 1 and the next reception/transmission are
started by using the receive completion interrupt INTCBnR, the reception/
transmission operations from the second time are not performed for 0.5
clocks of the SCKBn after the receive completion interrupt INTCBnR is
generated. To perform the continuous transfer, use the continuous transfer
mode.
4.
When CSIBn is operated in slave mode input an external clock via SCKBn
pin only after the transmission -/and/or reception process is started.
User's Manual U18743EE1V2UM00
Chapter 16
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