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Chapter 9
Table 9-5
(2)
Access
Address
Initial Value
Table 9-6
Bit position
Bit name
6 to 4
SUWL[2:0]
302
The base address PBA is calculated by
PBA = BPC.PA[13:0] x 2
Table 9-5 shows how the addresses of the programmable peripheral area are
assembled. The base address PBA is highlighted.
Address range of programmable peripheral area (12 KB)
31
...
28 27
0
...
0
...
0
...
0
0
...
0
VSWC - Internal peripheral function wait control register
The 8-bit VSWC register controls the bus access wait for the on-chip
peripheral I/O registers. The data wait states are based on the system clock.
Access to on-chip peripheral I/O registers is made in 3 clocks (without wait),
however, waits may be required depending on the operation frequency. Set the
values described below to the VSWC register in accordance with the operation
frequency used.
This register can be read/written in 8-bit units.
FFFF F06E
H
77
H
7
6
5
0
SUWL2 SUWL1 SUWL0
R
R/W
R/W
VSWC register contents (1/2)
Address setup wait for internal bus:
SUWL2
SUWL1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
Preliminary User's Manual U18743EE1V2UM00
14
...
BPC.PA[13:0]
...
BPC.PA[13:0]
BPC.PA[13:0]
4
3
2
0
VSWL2 VSWL1
R/W
R
R/W
Function
SUWL0
Number of address setup wait states
0
1
1 CPU system clock (VBCLK)
0
2 CPU system clock (VBCLK)
1
3 CPU system clock (VBCLK)
0
4 CPU system clock (VBCLK)
1
5 CPU system clock (VBCLK)
0
6 CPU system clock (VBCLK)
1
7 CPU system clock (VBCLK)
Bus Control Unit (BCU)
14 13
...
1
1
...
1
...
0
...
0
0
...
0
1
0
VSWL0
R/W
R/W
0
0
bit
1
1
0
PBA
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