NEC V850ES/F 3-L Series User Manual page 571

32-bit single-chip microcontroller
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CAN Controller (CAN)
Note
Note
Note
CCERC
Error counter clear bit
The CnERC and CnINFO registers are not cleared in the initialization
0
mode.
The CnERC and CnINFO registers are cleared in the initialization
1
mode.
1.
The CCERC bit is used to clear the CnERC and CnINFO registers for
re-initialization or forced recovery from the bus-off state. This bit can be set
to 1 only in the initialization mode.
2.
When the CnERC and CnINFO registers have been cleared, the CCERC
bit is also cleared to 0 automatically.
3.
The CCERC bit can be set to 1 at the same time as a request to change
the initialization mode to an operation mode is made.
4.
The CCERC bit is read-only in the CAN sleep mode or CAN stop mode.
5.
The receive data may be corrupted in case of setting the CCERC bit to (1)
immediately after entering the INIT mode from self-test mode.
AL
Bit to set operation in case of arbitration loss
Re-transmission is not executed in case of an arbitration loss in the
0
single-shot mode.
Re-transmission is executed in case of an arbitration loss in the
1
single-shot mode.
The AL bit is valid only in the single-shot mode.
VALID
Valid receive message frame detection bit
A valid message frame has not been received since the VALID bit was
0
last cleared to 0.
A valid message frame has been received since the VALID bit was last
1
cleared to 0.
1.
Detection of a valid receive message frame is not dependent upon storage
in the receive message buffer (data frame) or transmit message buffer
(remote frame).
2.
Clear the VALID bit (0) before changing the initialization mode to an
operation mode.
3.
If only two CAN nodes are connected to the CAN bus with one transmitting
a message frame in the normal mode and the other in the receive-only
mode, the VALID bit is not set to 1 before the transmitting node enters the
error passive state, because in receive-only mode no acknowledge is
generated.
4.
To clear the VALID bit, set the Clear VALID bit to 1 first and confirm that the
VALID bit is cleared. If it is not cleared, perform clearing processing again.
User's Manual U18743EE1V2UM00
Chapter 18
571

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