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Clock Generator
(5)
Entering subclock
mode
Note
Subclock mode
status
Table 4-33
MainOSC (f
)
X
SubOSC (f
)
XT
240 KHz internal oscillator (f
8 MHz internal oscillator (f
PLL (f
)
PLLO
CPU
Port function
Timer/counter
TAA0 -TAA4 Operable
TMM0
Watch Timer (WT)
Watchdog Timer (WDT2)
AD convertor
(c) Releasing by RESET input
The operation is the same as the normal reset operation.
Subclock operation mode
When the subclock operation mode is set, the CPU system clock f
changed from the main system clock to the subclock. Subclock can be f
f
. The selection is made by the SUBCLK bit of the option byte 007B
RL
Check that the CPU system clock has been changed by using the CLS bit of
the PCC register.
When the MCK bit of the PCC register is set to 1, the operation of the main
clock oscillator is stopped. Consequently, the entire system operates on the
subclock.
In the subclock operation mode, the subclock is used as the CPU system
clock, so that the current consumption can be reduced from that in the normal
operation mode. In addition, a current consumption close to that in the STOP
mode can be achieved by stopping the operation of the main clock oscillator.
The subclock operation mode is set when the CK3 bit of the PCC register is set
to 1 in the normal operation mode.
1.
Changing the value of the CK2 to CK0 bits of the PCC register is prohibited
when the CK3 bit is manipulated (0 to 1 or 1 to 0). Set the CK3 bit by using
a bit manipulation instruction. For details of the PCC register, refer to "PCC
- Processor clock control register" on page 173.
2.
If the following condition is not satisfied, change the CK2 to CK0 bits so as
to satisfy the condition and move to subclock operation mode.
Internal system clock (fCLK) > subclock (fSC) × 4
The following table shows the operation status in subclock mode.
Controller status in subclock mode (1/2)
With MainOSC operating
Oscillation enabled
Oscillation enabled
) Oscillation enabled
RL
)
Oscillation enabled
RH
Operable
Operable
Settable
Operable
Operable
Operable
Operable
User's Manual U18743EE1V2UM00
Working condition
With MainOSC stopped
Stops operation
Stops operation
Operable if f
RH
selected as count clock.
Operable if f
XT
clock.
Operable if f
RL
clock.
Stops operation
Chapter 4
is
VBCLK
or
XT
.
H
a
/8, f
/8, INTWT or f
is
RL
XT
is selected as count
is selected as count
207
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