NEC V850ES/F 3-L Series User Manual page 202

Chapter 4
IDLE2 mode status
Table 4-29
MainOSC (f )
X
SubOSC (f )
XT
240 KHz internal oscillator (f
8 MHz internal oscillator (f
PLL (f )
PLLO
CPU
Port function
Timer/counter TAA0 -TAA4 Stops operation
TMM0
Watch Timer (WT)
Watchdog Timer (WDT2)
a
AD convertor
Serial Interface UARTD0-2
CSIB0-1
IIC00
CAN Controller (CAN0)
Interrupt Controller
Key interrupting function
Clock Monitor
Power-On-Clear circuit
Low-Voltage Detector
Voltage Regulator
Internal data
a)
To achieve low power consumption, stop the A/D Converter before shifting to the IDLE2 mode.
Leaving IDLE2
mode
Note
202
The following table shows the operation status in the IDLE2 mode.
Controller status in IDLE2 mode
Without Subclock
Oscillation enabled
-
) Oscillation enabled
RL
) Oscillation enabled
RH
Stops operation
Stops operation
Holds status before IDLE2 mode is set
Operable if f /8, f
RH
selected as count clock.
Operable, if clocked by Prescaler3
Operable
Stops operation
UARTD0: Operable if ASCKD0 is selected as input clock
UARTD1-2: Operation stops
Operable, if SCKBn is selected as input clock.
Stops operation
Stops operation
Stops operation (But it is possible to leave IDLE2 Mode)
Operable
Operable
Operable
Operable
Operation continuous
The CPU registers, states, data and all other internal data such as the contents of
the internal RAM are retained as they were before IDLE2 mode was set
The IDLE2 mode is released by a non-maskable interrupt request signal (NMI
pin input or INTWDT2 signal), unmasked external interrupt request signal,
unmasked internal interrupt request of a peripheral function that can operate in
the IDLE2 mode, or reset signal.
When the IDLE2 mode has been released, the normal operation mode is
restored.
1. Interrupt request signals that are disabled by the NMI1M, NMI0M, and
INTM bits of the PSC register are invalid and do not release the IDLE2
mode.
2. When digital noise elimination is enabled for INTP3, the power save mode
cannot be released using INTP3 pin. For details, refer to "Pin Functions" on
page 31.
User's Manual U18743EE1V2UM00
Working condition
Oscillation enabled
/8 or INTWT is Operable if f
RL
selected as count clock.
Operable
Clock Generator
With Subclock
/8, f /8, INTWT or f
RH RL XT
is