NEC V850ES/F 3-L Series User Manual page 209

Clock Generator
Entering sub-IDLE
mode
Note
Sub-IDLE mode
status
Table 4-34
240 KHz internal oscillator (f
8 MHz internal oscillator (f
PLL (f )
PLLO
CPU
Port function
Timer/counter TAA0 -TAA4 Stops operation
TMM0
Watch Timer (WT)
Watchdog Timer (WDT2)
AD convertor
Serial Interface UARTD0-2
CSIB0-1
IIC00
CAN Controller (CAN0-3)
Interrupt Controller
Key interrupting function
Clock Monitor
Power-On-Clear circuit
Low-Voltage Detector
Voltage Regulator
Internal data
a)
Stop the PLL (PLLCTL.PLLON = 0) when you stop the main clock oscillation circuit.
the other on-chip peripheral functions stop operating. However, the on-chip
peripheral functions that can operate on the subclock continue operating.
The sub-IDLE mode can reduce current consumption more than the subclock
operation mode because the operations of the CPU, flash memory, and other
on-chip peripheral functions are stopped.
If the sub-IDLE mode is set after the main clock is stopped, a current
consumption close to that in the STOP mode can be achieved.
The sub-IDLE mode is set when the PSM1 and PSM0 bits of the PSMR
register are set to "10" and the STP bit of the PSC register is set to 1 while the
processor is in the subclock operation mode.
Insert five or more NOP instructions after the store instruction that manipulates
the PSC register to set the sub-IDLE mode.
The following table shows the operation status in sub-IDLE mode.
Controller status in sub-IDLE mode
When main clock oscillator oscillates
) Oscillation enabled
RL
) Oscillation enabled
RH
Operable
Stops operation
The settings of the previous mode are maintained
Operable if f /8, f
RH
Operable
Operable
Stops operation
UARTD0: Operable, if ASCKD0 is selected as input clock
UARTD1-2: Operation stops
Operable if SCKBn input clock is selected as operation clock.
Stops operation
Stops operation
Stops operation (but it is possible to leave Sub Idle Mode)
Operable
Operable
Operable
Operable
Operation continuous
The CPU registers, statuses, data and all other internal data such as the contents
of the internal RAM are retained as they were before Sub IDLE mode was set
User's Manual U18743EE1V2UM00
Working condition
Stops operation
/8 or f is selected as count clock.
RL XT
Operable if f
clock.
Operable if f
clock.
When main clock oscillator stops
a
is selected as count
XT
is selected as count
RL
Chapter 4
209